Design of Efficient Graph Based Algorithm With Modified Carry save Adder
نویسندگان
چکیده
منابع مشابه
Design of Area and Power Efficient Modified Carry Select Adder
Adders are one of the widely used digital components in digital integrated circuit design. The Carry Select Adder (CSA) provides a good compromise between cost and performance in carry propagation adder design. However, conventional CSA is still area-consuming due to the dual ripple carry adder (RCA) structure. In this paper, modification is done at gate-level to reduce area and power consumpti...
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In this paper, design of two different array multipliers are presented, one by using carry-look-ahead (CLA) logic for addition of partial product terms and another by introducing Carry Save Adder (CSA) in partial product lines. The multipliers presented in this paper were all modeled using VHDL (Very High Speed Integration Hardware Description Language) for 32-bit unsigned data. The comparison ...
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In this paper we investigate graph-based minimum-adder integer multipliers using carry-save adders. The previously proposed approaches use carry-propagation adders with two inputs and one output and are not suitable for carry-save adder implementation when we have a single input and a carry-save output of the multiplier. Using carry-save adders avoids carry propagation and will result in a high...
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According to the modern research the rapid development of portable electronics is forcing the designers to elevate the existing designs for better performance. Addition is the crucial arithmetic operation used in various applications like, Digital signal processors, ALUs, math processor and in various other scientific applications. In this paper, we proposed the 1-bit CSA with gates having diff...
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ژورنال
عنوان ژورنال: International Journal of Mechanical Engineering
سال: 2014
ISSN: 2348-8360
DOI: 10.14445/23488360/ijme-v1i1p102